This invention relates to a manufacturing method for a MOSFET type integrated circuit having a relatively short channel, whose source and drain electrodes are connected electrically to source and drain regions in a semiconductor substrate.
A structure of a prior art MOSFET is shown in FIG. 1. The structure is formed using the following process: First, a thick insulation layer (2) made of SiO.sub.2 is selectively formed on a P type semiconductor substrate (1) made of Si. A thin insulation layer and a polycrystalline silicon (Poly-Si) layer are formed on the exposed surface of the substrate (1). The thin insulation layer and the polycrystalline silicon layer are removed selectively through a photo engraving process, and become gate insulation layer (3) and gate electrode (4), respectively. N type impurities are implanted in substrate (1) using a mask on the gate insulation layer (3) and the gate electrode (4). The implanted N type impurities are activated in a heating step and source and drain regions (5) and (6) are thus formed. Next, an insulation layer (7) made of SiO.sub.2 is deposited on the entire surface and contact holes (8) and (9) are formed by a photo engraving process. A layer of Al is deposited on the whole surface including the contact holes (8) and (9). The Al layer is patterned by a photo engraving process, selectively removed, and source and drain electrodes (10) and (11) are thus formed. In this process, the source and drain regions (5) and (6) must have a high concentration of impurities in order to obtain favorable ohmic contact with the Al electrodes. And it is desirable that the source and drain regions (5) and (6) are formed deeper. However, Al electrodes (10) and (11) can penetrate as a spike into the source and drain regions (5) and (6) by a eutectic reaction of Al and Si, make contact with the P type substrate (1), and destroy the function of MOSFET. And, the deeper source and drain regions (5) and (6) are formed using conventional processes, the more the diffusion of impurities in the lateral direction is increased. This increased lateral diffusion has the disadvantage of unnecessarily decreasing the effective channel length and prevents a fine structure from being achieved because the gate electrode must be formed larger to prevent this occurrence. This increased lateral diffusion also can cause the fluctuation of the threshold voltage because it is very difficult to control the extent of the diffusion in the lateral direction. Furthermore, the depletion layer of the drain region may reach the source region in a operating state, a "punch-through" phenomenon, and the MOSFET device may not operate with a predetermined characteristic.
Source and drain regions (5) and (6) can be formed shallower than those of FIG. 1 using prior art processes. In the resulting MOSFET device which is depicted schematically in FIG. 2, source and drain electrodes (10) and (11) still can reach the substrate (1) because they penetrate as a spike into the source and drain regions (5) and (6) as a result of the eutectic reaction of Al and Si. However, the sheet resistivity of the source and drain regions becomes high because these regions are formed shallower and cannot be formed with high concentration of impurities. Furthermore, when source and drain regions (5) and (6) are formed in a fine pattern using conventional processes, source and drain electrodes (10) and (11) can be formed with a gap in mask alignment, and this problem is depicted in FIG. 3. In this situation contact hole (9) may not be formed solely on the drain region (6) but may be formed on the intersection of the drain region (6) and substrate (1). As a result, drain electrode (11) can become shorted to substrate (1), and the MOSFET can lose its intended function.